Mobiles devices imply high constraints in the embedded power management unit. Typically, these power management units are comprised of buck convertors which are synchronized by a main clock phased by a pulse width modulated (PWM) control. FIG. 1 illustrates such a conventional architecture.
The main clock 1 (CLK) is phase shifted by the blocks 2, 3, 4 (PH1, PH2, PH3). Each of these blocks shifts the clock phase by a different value so as to produce 3 different clocks, CLK_1, CLK_2, CLK_3. Each of these clocks drives a respective one of the buck convertors 5, 6, 7, respectively BUCK1, BUCK2, BUCK3. In the basic example of the FIG. 1, only 3 bucks 5, 6, 7 are depicted. The blocks PH1, PH2, PH3 can thus force a 60° phase shift between the clocks. For instance:                The clock CLK_1 may not be shifted with regard to the main clock CLK.        The clock CLK_2 may be shifted by +60°, with regard to the main clock CLK.        The clock CLK_3 may be shifted by +120° with regard to the main clock CLK.        
In general where N is the number of buck convertors, the clock CLK_i driving the buck convertor BUCK_i may be shifted by 360×i/N, where iε[0, N−1]. This architecture prevents all the buck convertors starting their conduction cycle on the same clock rising edge, which would lead to a large undershoot on the battery. For this reason, the buck convertors are often referred to as PWM synchronized voltage mode control.
FIG. 2 shows a high level block diagram of a standard synchronized PWM voltage mode control DC/DC architecture. The output voltage Vout is compared with the reference voltage Vref and amplified by a compensation network made of resistors Z1, Z2, capacitor c and an amplifier (Amp). The passive elements Z1, Z2 are dedicated to the stabilization of a global loop. At the output of the amplifier (Amp), the signal Verror is compared to an internal ramp (Vramp), which is synchronized to the rising edge of the clock signal.
At the beginning of the clock signal, the state machine SM operates a latch L1 to power PMOS 8 on to conduct the clock signal will synchronously keep the NMOS 9 non-conducting (off). Each time the error signal Verror crosses the Vramp signal, the state machine turns the PMOS 8 off and switches a latch L2 to power on an NMOS 9 to the conducting state. The end of the NMOS conduction cycle is set by the signal Vx at the end of the clock cycle. This is further illustrated by the FIG. 3 which shows the time lines for, from top to bottom, the clock 10, the signal Vx 11, the ramp Vramp 12 and the error signal Verror 13, and the output of the PMOS and NMOS, respectively CMD_P 14 and CMD_N 15.
An important drawback of this architecture is that in case of high output load transients, the output voltage undershoots. The load transient performance is dependent not only on the output filters L and C but also on the phase difference between (ΔTd) the output load transient step and the clock rising edge. Due to the dependence on the phase difference between the output load transient step and the clock rising edge, the load transient performance can be impacted by 30%.
High output load transients are more and more a requirement from the market. There is therefore a need for a technical solution which will reduce the impact on the performance of high output load transients.